1. Field of the Invention
The present invention relates to a PLL circuit.
2. Description of the Related Art
In recent years, an information recording device that writes and reads out data to and from a recording medium such as an optical disc (for example, a CD-R, a DVD-R/RW) obtains a rotation synchronizing signal of the recording medium, extracts a synchronous clock based on the signal, and uses this clock as a recording clock when performing data recording processing. Generally, a PLL (Phase Locked Loop) circuit is used for extracting such a periodic clock.
In Japanese Patent Laid-Open No. 2000-4156, a PLL circuit having automatically selectable VCO properties is described as shown in FIG. 1 of Japanese Patent Laid-Open No. 2000-4156. In the PLL circuit, a phase comparator 2 compares the phase of a reference input from an input terminal 1 and that of an output clock fed from a frequency divider 6, and supplies the error signal to a direct current amplifier 3. The direct current amplifier 3 amplifies the supplied error signal, and supplies the amplified signal to a low-pass filter 4. The low-pass filter 4 filters an unnecessary-frequency component from the supplied error signal, and supplies the resulting signal to a voltage-controlled oscillator 11. The voltage-controlled oscillator 11 oscillates the output clock having a frequency based on a selected VCO property according to the supplied error signal, and supplies the clock to the frequency divider 6. The frequency divider 6 divides a frequency of the supplied output clock, outputs the clock from an output terminal 7, and also feeds back the clock to the phase comparator 2.
Here, as shown in FIG. 2 of Japanese Patent Laid-Open No. 2000-4156, the voltage-controlled oscillator 11 in Japanese Patent Laid-Open No. 2000-4156 has a plurality of different VCO properties so as to satisfy a desired frequency range. In Japanese Patent Laid-Open No. 2000-4156, it is described that one of these VCO properties is, selected.
Specifically, in the PLL circuit shown in FIG. 1 of Japanese Patent Laid-Open No. 2000-4156, an upper-limit-voltage comparator 15 and a lower-limit-voltage comparator 16 compare and determine whether the error signal filtered by the low-pass filter 4 is in the range from the upper limit voltage to the lower limit voltage shown in FIG. 2 of Japanese Patent Laid-Open No. 2000-4156. The upper-limit-voltage comparator 15 and the lower-limit-voltage comparator 16 supply the determination signal to a VCO property switcher 17. The VCO property switcher 17 does not switch a VCO property when an error signal is at a point A within the range from the upper limit voltage to lower limit voltage shown in FIG. 2 of Japanese Patent Laid-Open No. 2000-4156. The VCO property switcher 17 switches to a VCO property having a higher oscillation frequency according to a control voltage than that of the selected VCO property, when an error signal is at a point B that is the upper limit voltage or greater shown in FIG. 2 of Japanese Patent Laid-Open No. 2000-4156. The VCO property switcher 17 switches to a VCO property having a lower oscillation frequency according to a control voltage than that of the selected VCO property, when an error signal is at a point D that is the lower limit voltage or less shown in FIG. 2 of Japanese Patent Laid-Open No. 2000-4156.
Thus, according to Japanese Patent Laid-Open No. 2000-4156, it is possible to automatically switch to the optimal VCO property according to an error signal, and control it.
In Japanese Patent Laid-Open No. 11-195983, a charge pump phase locked loop 300 is described as shown in FIG. 3 of Japanese Patent Laid-Open No. 11-195983. In this charge pump phase locked loop 300, a phase/frequency detector (PFD) 302 compares the phase of an input signal FIN with the phase of a feedback signal FFB when performing a usual PLL operation. According to a result of the comparison, the PFD 302 generates an error signal, which is either an up signal U or a down signal D, and supplies the signal to a charge pump 304. Depending on whether the error signal is the up signal or the down signal, the charge pump 304 applies charge to a capacitance of a loop filter 306, or removes charge from the capacitance, and generates a loop filter voltage VLF. The loop filter 306 supplies the loop filter voltage VLF to a voltage-controlled oscillator 308 via a switch SW1 that has been turned on. The voltage-controlled oscillator 308 generates and outputs an internal signal FOSC determined based on a selected VCO operating curve, according to the supplied loop filter voltage VLF.
Here, the voltage-controlled oscillator 308 shown in FIG. 3 of Japanese Patent Laid-Open No. 11-195983 has many VCO operating curves as shown in FIG. 2 of Japanese Patent Laid-Open No. 11-195983 similar to the voltage-controlled oscillator 108 shown in FIG. 1 of Japanese Patent Laid-Open No. 11-195983. In Japanese Patent Laid-Open No. 11-195983, it is described that one VCO operating curve is selected (trimmed) among many VCO operating curves using a special digital control input value N.
Specifically, in the charge pump phase locked loop 300 shown in FIG. 3 of Japanese Patent Laid-Open No. 11-195983, when automatically trimming, the switch SW1 is opened, and a switch SW2 is closed. A reference voltage VREF is supplied to the voltage-controlled oscillator 308, instead of a loop filter voltage VLF. The charge pump 304 supplies a loop filter voltage VLF to a state machine 316. The state machine 316 sequentially selects a digital control input value N and supplies the value to the voltage-controlled oscillator 308, so as to sequentially select a different VCO operating curve. The state machine 316 detects that a loop filter voltage VLF has converged on a suitable quiescent potential (either grounding or VDD). According to this detection, the state machine 316 specifies two VCO operating curves that have center frequencies just above and just below the frequency of an input signal FIN, and selects one of the two specified VCO operating curves for use when performing an usual PLL operation.
Thus, according to Japanese Patent Laid-Open No. 11-195983, a suitable VCO operating curve can be automatically selected.
Now, consider a PLL circuit comprising a phase comparator, a charge pump circuit, a low pass filter, a voltage-controlled oscillator (VCO circuit), and a frequency dividing circuit. The loop properties of this PLL circuit are determined based on the gain property and frequency property of a circuit to be configured, and by appropriately designing these Properties, a property such as the lock-in time necessary for a phase to be locked or the jitter can be as desired. Particularly, regarding the gain property of these PLL properties, the gain property of the VCO circuit becomes dominant.
The gain property of a VCO circuit (control voltage-oscillation frequency property) changes due to variations in power supply voltages and manufacturing processes. When the VCO circuit has a high gain, the change in the oscillation frequency due to extraneous noise being superposed on a control voltage input into the VCO circuit becomes large, so as to increase jitter. On the other hand, when the VCO circuit has a low gain, even with the upper limit within the settable range of the control voltage determined based on the power supply voltage or a circuit configuration, the oscillation frequency of a signal output from the VCO circuit may not reach a desired frequency. Consequently, when the gain of a VCO circuit varies with respect to a designed value, due to the increase in jitter or lock-in time, the PLL properties may not be as desired.
In Japanese Patent. Laid-Open No. 2000-4156, as shown in FIGS. 8 and 9 of Japanese Patent Laid-Open No. 2000-4156, it is described that variations in gains within the range between the upper limit voltage and the lower limit voltage of a desired frequency range are allowed with respect to the control voltage to the VCO circuit when the circuit is locked. Accordingly, the gain of the corrected VCO circuit is allowed to have a certain amount of variation; thus, the PLL properties may not be desired properties.
In Japanese Patent Laid-Open No. 11-195983, as described above, it is described that one VCO operating curve is selected from among many VCO operating curves. Due to variations in the gain properties, or the like, a VCO operating curve corresponding to desired PLL properties may not exist among these many preset VCO operating curves. In this case, even when one VCO operating curve is selected from among many VCO operating curves, the PLL properties may not be desired properties.
Further, in Japanese Patent Laid-Open No. 11-195983, it is described that one operating curve with which a loop filter voltage VLF converges on a quiescent potential (either grounding or VDD) is selected from among many operating curves. In this case, since a voltage that is different from that at the time of automatic trimming is input into the voltage-controlled oscillator 308 of Japanese Patent Laid-Open No. 11-195983 at the time of a usual PLL operation after the automatic trimming has been performed; thus, the PLL circuit may not operate based on the desired properties.